1. Field of the Invention
This invention relates to a storage-type two-dimensional image sensing device for plural interlacing, where data of each photo-diode is once stored and then output in parallel. More particularly, this invention relates to an infrared image sensor.
2. Description of the Related Art
FIG. 1 schematically illustrates a typical prior art circuit configuration of a two-dimensional image sensing device of a storage type, where in order to simplify the drawing there are drawn only 36 (=6.times.6) photo-diodes 3.sub.11 . . . 3.sub.66 arranged in a matrix and their associated CCD (charge-coupled device) circuits for storing the data output from each photo-diode and then outputting in parallel the stored data of photo-diodes on a single horizontal line. FIG. 2 schematically illustrates a timing chart of the FIG. 1 prior art circuit.
Each of input gate line 4 and each of storage gate lines 5 is applied with DC biases V.sub.IG and v.sub.SG, respectively. On an application of a transfer gate signal .phi.TG via each transfer gate line 6 to each transfer gate electrode, signal charges generated in each of all the photo-diodes 3.sub.11. . . 3.sub.66 is concurrently transferred to and stored in an associated storage gate SG of each photo-diode. Next, on sequential application of scan signal .phi.V1, .phi.V2 . . . .phi.V6 output from a vertical scan shift register 1, to gate electrodes of output switches SW1 . . . SW6, the electric charges stored in each storage gates SG on a single horizontal line are output via each vertical signal line VSL in parallel to a horizontal read-out circuit 2. Next, thus input data is serially output for each horizontal line to an amplifier 8 as data of each line. The operation is repeated for each frame.
In recent years, it has been seriously required to increase the number of pixels, i.e. number of photo-diodes, of two-dimensionally arranged image sensing device. Then, in order to increase the pixel number without increasing the overall chip size, the element size as well as the element pitch have to be reduced. However, the size reduction of input gate IG, transfer gate TG and output switch SW has already arrived to their minimum limits. Therefore, the storage gate has to suffer the size reduction. According to thus reduced size of the storage type sensor the duration of the charging period, that is, charge integration time Tint, has to be reduced, resulting in reduced electric charge stored in each pixel. This is because the charge integration is approximately proportional to the charging period Tint.
Thus, if the size reduction is really carried out according to the FIG. 1 prior art circuit configuration, the reduced storage gate area worsens the sensitivity, the dynamic range of the detected light, and also the signal-to-noise ratio S/N because the signal-to-noise ratio is determined by the square root of the quantity of the stored charge. If the integration period Tint is not reduced even though the storage gate area is reduced, the electric charge delivered from a photo-diode to which a high temperature IR (infrared) light is injected overflows the storage gate. Consequently, there causes a problem in that the detectable temperature range, i.e. the dynamic range, is limited.